Due to their favorable electron transport properties, the use of III-V semiconductor materials (i.e., materials that include at least one group III element and at least one group V element) has been proposed for future generations of metal oxide semiconductor field-effect transistor (MOSFET) devices. See, for example, del Alamo et al., “The Prospects for 10 nm III-V CMOS,” VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium, pgs. 166-167 (April 2010) (hereinafter “del Alamo”).
There are, however, some notable challenges associated with the fabrication of III-V FET devices. For instance, with the aggressive scaling requirements of current CMOS technology, self-aligned contact schemes with low contact resistance are needed. However, no such techniques currently exist to achieve these goals. For example, III-V FET devices with self-aligned contacts were demonstrated in Kim et al., “Self-aligned metal Source/Drain InxGa1-xAs n-MOSFETs using Ni—InGaAs alloy,” IEDM 2010 (hereinafter “Kim”), however, they resulted in a very large external resistance, i.e., 38.7 kilo-ohm-micron2 (kΩμm) in the case of In0.53Ga0.47As. The best contact resistance achieved for In0.8Ga0.2As with bandgap less than 0.5 electron volt (eV) was 2.73 kΩμm (see, e.g., del Alamo), which results in poor performance of 4 microamps per micrometer (μA/μm) for 500 nanometer (nm) devices.
Therefore, improved techniques for producing self-aligned contacts in III-V semiconductor FET devices would be desirable.